1. Field of the Invention
The present invention relates to a data processing circuit provided in a player or the like which is used for a recording medium such as CD-ROM, CD-R, CD-DA, CD-RW, the data processing circuit processing data read from the recording medium or processing data to be written onto the recording medium.
2. Description of the Related Art
In a recording medium such as a CD-ROM, data is recorded in a predetermined format for each frame. The format has a form in which head data, user data, synchronizing data, other various data and subcode data are stored in the stated order. For the subcode data and user data, a mutual time relationship should be maintained. When the user data and subcode data are managed in a linear buffer area, management table information is prepared specially (see Japanese Laid-Open Patent Application No. 2-310658).
However, when the management table information is provided specially, and a system control unit refers to this table information and performs necessary control, the load of the system control unit increases, and it is difficult to cope with high-speed processing such as processing for an 8-time speeds, a 10-times speed or the like.
Therefore, the applicant of the present application, in consideration of the above-mentioned situation, proposed, previously, in Japanese Laid-Open Patent Application No. 10-302389, a data processing circuit, an object of which is to eliminate necessity of the management table information by maintaining the time relationship of data in a page unit, to reduce the load of the system control unit, and to improve the memory use efficiency, in a case where processing is performed in a page unit, by providing a page region and a buffer region separately.
This data processing circuit will now be described based on FIGS. 1-10C.
FIG. 1 shows a block diagram of the data processing circuit 100 and peripheral circuits thereof. The data processing circuit 100 is connected to a system controller 17, an AT attachment (ATA) 18, and a digital signal processor (DSP) 19. The data processing circuit 100 performs writing/reading of signals on a DRAM 2, which acts as a buffer memory, and transfer of these signals between the DRAM 2, and the system controller 17, AT attachment (ATA) 18 and digital signal processor (DSP) 19. The data processing circuit 100 includes various masters (which are main processing circuits, and specific names and functions of which will be described later) 3-7, a buffer manager 16 and a DRAM controller 1.
The system controller 17 controls the data processing circuit 100, transmits data to and receives data from a system controller interface (system controller IF) 3 which is a master. The AT attachment 18 forms a host bus, and transmits data to and receives data from a host interface (host IF) 4 which is a master. The digital signal processor (DSP) 19 divides data, which is transmitted from an EFM (Eight-to-Fourteen Modulation) processing unit, not shown in the figure, into CD-DA data and the subcode data. The digital signal processor 19 provides the CD-DA data in the form of serial data to a CD-DA interface (CD-DA IF) 6, which is a master, and provides the subcode data in the form of serial data to a subcode interface (subcode IF) 7, which is a master, at the time of decoding. The digital signal processor 19 combines the CD-DA data provided by the CD-DA interface 6 and the subcode data provided by the subcode interface 7, and transmits the combination to the EFM processing unit. However, there is a type of the DSP in which the main data and subcode data are outputted in parallel using a bus through the DSP.
As shown in FIG. 2, the DRAM 2 is used after being divided into a paging area and a buffering area, through processing by the data processing circuit 100. Pages 0 through n (the size of the page being fixed) are allocated to the paging area, and page n+1 and the subsequent pages (the size of the page not being fixed) are allocated to the buffering area. In each page, various data for one sector of a recording medium such as a CD-ROM or a CD-DA can be stored. FIG. 2 will be described in detail later.
The system controller interface 3, which is the master, performs processing such as transferring data, transferred from the system controller 17, to one page of an area which is indicated by the value stored in a system buffer page (SysBufPage) 8, and so forth.
A sector processor 5, which is a master, is a processing block which performs EDC (error correction)/ECC (error detection) on data for a CD-ROM, for example. The sector processor performs processing of the data stored in one page of an area indicated by the value stored in a sector processor buffer page (SPBufPage) 11.
The CD-DA interface (CD-DA IF) 6, which is the master, performs processing such as storing serial data transmitted from the digital signal processor 19 in one page indicated by the value stored in a CD buffer page (CDBufPage) 12. At the time of storing, in a case of CD-ROM data, the sync pattern of one block is detected, and control is performed such that one block corresponds to one page.
The subcode interface (subcode IF) 7, which is the master, performs processing such as storing serial data for the subcode data, inputted from the digital signal processor 19, in one page indicated by the value stored in a subcode buffer page (SubBufPage) 13, and so forth. However, there is a type of the DSP in which the data is not serial data. At the time of storing, the sync pattern of the subcode data is detected for each frame, and control is performed such that one frame corresponds to one page.
The host interface (host IF) 4, which is the master, performs processing such as transferring the data, transferred from a host bus such as the AT attachment 18, an SCSI, or the like, to one page indicated by the value stored in a host buffer page (HstBufPage0) 9a, for each sector, and so forth. The host can access a buffering area, which will be described later. For indicating the page, a host buffer page (HstBufPage1) 9b is prepared.
The buffer manager 16 includes page controllers (page control) 14, connected to the masters 3, 4, 5, 6 and 7, respectively, various page registers (specific names thereof will be described later) 8, 9a, 9b, 11, 12 and 13, address generators (address generate) 15, connected to the masters 3, 4, 5, 6 and 7, and to the page registers corresponding thereto, respectively, and a ring-end-page (RingEndPage) storing unit 10 which stores therein the ring end page (‘n’ in the example of FIG. 2). The buffer manager performs arbitration of access from the masters 3, 4, 5, 6 and 7, and generation of addresses (current address) for the DRAM controller 1. Specifically, each master makes an access request to the buffer manager 16 by expressing a request. When multiple requests are made by the respective masters simultaneously, the buffer manager 16 performs arbitration through priority control, and returns an acknowledgement signal (ack) to one master. Thereby, the buffer manager 16 performs data access for this master. Each master can inform the buffer manager 16 of a page-register updating request by expressing increase (inc). Each page controller 14, when receiving this updating request, refers to the ring end page stored in the ring-end-page storing unit 10, and performs updating of the value stored in the respective page register.
The DRAM controller 1 is connected with the masters 3, 4, 5, 6 and 7 via data lines, and, also, in response to a request from the buffer manager 16, generates various signals and addresses for controlling the DRAM 2. Then, the DRAM controller 1 transmits data to and receives data from the master which has made the request. The DRAM controller 1 performs 8-bit data transfer between the DRAM controller 1 and the system controller interface 3. The DRAM controller 1 performs 16-bit data transfer between the DRAM controller 1 and each of the other masters.
FIG. 2 illustrates how each master accesses buffer data. Each master manages data to be currently processed in a page unit. As described above, the arrangement of the buffer RAM of the DRAM 2 is such that the area indicated by page 0 through page n (n is the value of the ring end page) is referred to as the paging area, and the area indicated by page n+1 through the last page (the last of the mounted memory) is referred to as the buffering area. Whether it is possible to access only the paging area, whether it is possible to access both the paging area and buffering area, and whether there is a difference between the time of decoding and the time of encoding in the case where it is possible to access both the paging area and buffering area, for each master, are indicated in TABLE 1, shown later. The master, which can access only the paging area, processes page 0, when the processing up to page n is finished. The processing therefor is performed by the page register corresponding to this master. The master, which can access the buffering area, can process the page n+1. FIG. 2 shows the state at the time of decoding. The CD-DA interface 6 and subcode interface 7 write data, read from the recording medium, to page 0, page 1, page 2, . . . , in sequence (FIG. 2 shows the state in which writing to page 2 is currently performed). The sector processor 5 accesses page 0, page 1, page 2, . . . , to which data was already written, and reads the data, performs error correction on the data, and returns the data (FIG. 2 shows the state in which processing of page 1 is currently performed). FIG. 2 shows the state in which the AT attachment 18 accesses page 0 via the host interface 4, and receives the data obtained as a result of the correction being performed.
FIG. 3A shows the arrangement of the buffer RAM in the DRAM 2. FIG. 3B shows a data format in a page in the case of CD-ROM. FIG. 3C shows a data format in a page in the case of CD-DA. The amount of 3072 bytes is allocated to each page, and the user data and the subcode data are stored therein. The amount of data stored in each page is smaller than the size of the page, and, in the figures, 288 bytes are not used. 96 bytes are used for the subcode data, which includes data expressed by symbols such as P, Q, R, S, T, U, V and W. The details thereof will be described later.
The following TABLE 1 clarifies the offset, access area, and so forth of each master.
TABLE 1Access areaMasteroffsetPageRegisterPagingareaBufferingareaCD-DA0x000-0xA56CDBufPage◯XIFSector0x000-0xA56SPBufPage◯XProSub-0xA70-0xADFSubBufPage◯XDec , ◯EnccodeIFHost0x000-0xFFFHstBufPage0, 1◯◯IFSys Con0x000-0XFFFSysBufPage◯◯IF
FIG. 4 is a flowchart showing page-register updating control in the page controller 14, in the case where the master is the CD-DA interface 6. After initial setting (in a step S1), it is determined (in a step S2) whether there is a page-register updating signal (inc) from the master. When it is determined that there is the page-register updating signal, it is determined (in a step S3) whether the current value of the CD buffer page (CDBufPage) 12 is smaller than the value of the ring end page (RingEndPage) 10. When the current value of the CD buffer page 12 is smaller than the value of the ring end page 10, the value of the CD buffer page 12 is incremented by 1 (in a step S4). When the current value of the CD buffer page 12 is not smaller than the value of the ring end page 10, the value of the CD buffer page 12 is updated to be 0 (that is, 0x000), and, also, the CD buffer flag (CDBufFlg) toggles (from 0 to 1, from 1 to 0) (in a step S5).
FIG. 5 is a block diagram showing connection relationship, in the case where the master is the system controller interface (system controller IF) 3, for example, of the corresponding system buffer page (SysBufPage) 8, address generator 15 and DRAM controller 1. In the figure, A[11:0] is address information (information indicating the specific address in the page) which is provided from the system controller interface 3 to the buffer manager 16. D[7:0] is data which is provided from the system controller interface 3 to the DRAM controller 1 through the data line. The address information (address for specifying the page) of the significant 13 bits of the system buffer page (SysBufPage) 8 is added to the address of the 12 bits of the above-mentioned A[11:0], as shown in the figure. Thus, the address of 24 bits, for accessing the DRAM 2, is generated. Further, a request control unit 3a of the system controller interface 3, based on access signals (CS1B, REB, WEB), generates a request signal (REQ), and accesses the DRAM controller 1. The same arrangement is provided for each of the other masters.
FIG. 6 illustrates a signal flow in the case where decoding processing is performed in the data processing circuit 100 shown in FIG. 1. In the decoding processing, data read out from the recording medium is provided to the data processing circuit 100 via the DSP 19 as CD-DA input and subcode input, and, then, is provided to the AT attachment 18 via the data processing circuit 100 and DRAM 2. This data (approximately 3 kilobytes) is in synchronization with a block synchronizing signal (BSYC), and is stored in the pages indicated by the CD buffer page (CDBufPage) and in the pages indicated by the subcode buffer page (SubBufPage) (see (a), (b), (c), (d) and (e) in the figure). The values stored in the pages indicated by the sector processor buffer page (SPBufPage) correspond to the values stored in the pages which are previous to the pages indicated by the CD buffer page (CDBufPage), respectively, (see (f) and (g) in the figure) because the sector processor performs error detection and so forth using the already-written data. The degree of this page lag may be any degree as long as catching up is prevented.
The system controller interface (system controller IF) 3 stores, in the buffering area, the necessary part (for example, approximately 2 kilobytes) of data which has been processed by the sector processor. For this purpose, the system controller interface 3 performs a reading operation at the value corresponding to the page previous to the page indicated by the sector processor buffer page (SPBufPage), and performs an operation of writing, into the n+1 page of the buffering area, the above-mentioned necessary part of the data which has been processed by the sector processor (see (h) and (i) of the figure). In order to read out the data obtained as the result of the correction being performed and stored in the buffering area, and, then, to provide it to the AT attachment 18, the host interface (host IF) 4 reads out the data from the above-mentioned n+1 page of the buffering page at the transfer commencement address specified by a transfer counter provided in the page controller 14 for the host interface 4 and the HstBufPage1 (which functions as a page specifying buffer for the buffering area at the time of decoding) (see (j) and (k) of the figure). When finishing the processing for the current page, each master outputs the increment (inc) signal so as to cause the respective one of the page controllers 14 to perform page updating processing.
FIG. 7 illustrates a signal flow in the case where encoding processing is performed in the data processing circuit 100 shown in FIG. 1. In the encoding processing, the data provided by the AT attachment 18 is provided to the DSP 19 (EFM encoder) through the data processing circuit and DRAM 2. The host interface (host IF) 4transfers the data to the page indicated by the host buffer page (HstBufPage0) (see (a) and (b) of the figure). The other masters are controlled so as to complete the processing in a page unit for each ESFS (Encode Subcode Frame Sync) which is a one-sector processing unit outputted by the CD encoder (see (e) of the figure). In order for the sector processor 5 to perform parity-adding processing using the data which was already written by the host interface 4, the sector processor buffer page (SPBufPage) has the value corresponding to the page previous to the page indicated by the host buffer page (HstBufPage0) (see (c) and (d) of the figure).
Then, in order to provide the data obtained as a result of being processed by the sector processor 5 to the DSP 19 (EFM encoder), the CD-DA interface 6 performs a reading operation at the value of the CD buffer page (CDBufPage) corresponding to the page previous to the page indicated by the sector processor buffer page (SPBufPage) (see (f) and (g) of the figure). In (g) of the figure, Trn0, Trn1, . . . represent the data corresponding to the CD-ROM sectors, respectively. Similarly, in order to provide the data obtained as the result of being processed by the sector processor 5 to the DSP 19 (EFM encoder), the subcode interface (subcode IF) 7 performs a reading operation at the value of the subcode buffer page (SubBufPage) corresponding to the page previous to the page indicated by the sector processor buffer page (SPBufPage) (see (h) and (i) of the figure). In (i) of the figure, each of Trn0, Trn1, . . . represents the data corresponding to 96 bytes of the subcode frame.
The EFM encoder performs EFM modulation on the combination of the above-mentioned CD data and subcode data, converts the thus-modulated data into serial data, and outputs the thus-obtained data to a laser pickup (not shown in the figures) so that this data will be written in a recording medium.
Thus, the buffer RAM is divided into the paging area and buffering area, and, at the time of decoding, the data (the amount of which is smaller than the amount of data which was stored in the original page (from approximately 3 kilobytes to approximately 2 kilobytes)) which is needed by the AT attachment is stored in the buffering area. Thereby, the use efficiency of the memory can be very improved.
At the time of encoding, the data provided by the AT attachment 18 is stored in the predetermined pages in the buffer RAM of the DRAM 2, each master accesses the pages and processes this data, in sequence, and, finally, the data to be provided to the EFM encoder is outputted serially. At this time, originally, in each page, all of the subcode data is stored together with the user data which is the main data. The subcode data consists of the data expressed by the symbols such as P, Q, R, S, T, U, V and W. In particular, the subcode Q data is information relating to the time, and can be automatically generated. However, in order to generate the subcode Q data in the page of the paging area, it is necessary to access this page frequently. As a result, the frequency of access arbitration between the masters increases, and the processing-speed decreases. Furthermore, in an arrangement in which a circuit for storing this subcode Q data in the page is needed, the circuit becomes complicated. Further, the subcode P data is information, for example, relating to a portion between two adjacent tunes, is either 0 or 1 in the subcode data (96 bytes) in one sector, and can be generated automatically. However, it is necessary to perform frequent access in order to thus store the same data in the 96 bytes. As a result, the frequency of access arbitration between the masters increases, and the processing speed decreases. Furthermore, in an arrangement in which a circuit for storing this subcode P data in the page is needed, the circuit becomes complicated.
How to utilize the above-mentioned buffering area also at the time of encoding will now be described. FIG. 8 shows an arrangement in which the original data of the subcode Q data and subcode P data of the subcode data is generated in the buffering area (this data being referred to data for automatic generation, and the reference numeral 30 being given thereto in the figure), and, at the time of encoding, this data for automatic generation is outputted together with the other subcode portion. The data for automatic generation 30 includes Cont/Adr for providing a meaning to each group (TNO, INDEX, or the like) and so forth, TNO having information such as which track number the first tune starts from, for example, INDEX having predetermined information, relative time (RMIN, RSEC, RFRAME), ZERO, absolute time (AMIN, ASEC, AFRAME), MODE, REPEAT, POINT, and PMSB. One second corresponds to 75 frames (sectors). The absolute time can be automatically generated only as a result of the start time being determined. The relative time can also be automatically generated only as a result of the initial value being determined.
This automatic generation will now be described in detail using FIGS. 8, 9A, 9B, 9C, 9D, 9E, 10A, 10B and 10C. FIG. 9A shows the arrangement of the buffer RAM, FIG. 9B shows the arrangement of one page, FIG. 9C shows the arrangement of the buffering area for the subcode data (in which area the commands for obtaining the data for automatic generation 30 are written), FIG. 9D shows the data for automatic generation 30, and FIG. 9E shows the subcode data in the page. FIG. 10A shows, as does FIG. 9E, the subcode data in the page, FIG. 10B shows, as does FIG. 9D, the data for automatic generation, and FIG. 10C shows the arrangement of output data which is obtained as a result of the data for automatic generation 30 being incorporated with the other subcode portion (P, R through W or R through W).
(Subcode Q Data Generation)
The subcode Q data for each frame is generated using the data for automatic generation 30. The data for automatic generation 30 is formed in a unit of 16 bytes (offset: 0x00 through 0x0F). Because FIG. 8 shows the case at the time of encoding, the areas 0x0A and 0x0B relating to CRC are omitted in the figure.
In an RTIM counter 31, a ZERO counter 32 and an ATIM counter 33, the data of the offsets 0x03 through 0x09 (RMIN through AFRAME) is stored as the initial values when load=1 (a predetermined bit in the 8-bit data stored in MODE is 1). On the other hand, when load=0 (the predetermined bit in the 8-bit data stored in MODE is 0), depending on whether a predetermined bit of the 8-bit data stored in MODE is 0 or 1 (or, 1 or 0), incrementing/decrementing is performed for each frame. When REPEAT=0 where REPEAT is decremented for each frame, processing is performed on the data for automatic generation in the buffering area indicated by the n (ring end page)+1 and POINT (see FIGS. 9A-9E).
When RTIMselect=1 (a predetermined bit in the 8-bit data stored in MODE is 1), a selector 34 selects the value of the RTIM counter 31, and outputs the selected value as data to be used for forming encode subcode Q data 37.
When ZEROselect=1 (a predetermined bit in the 8-bit data stored in MODE is 1), a selector 35 selects the value of the ZERO counter 32, and outputs the selected value as data to be used for forming the encode subcode Q data 37.
When ATIMselect=1 (a predetermined bit in the 8-bit data stored in MODE is 1), a selector 36 selects the value of the ATIM counter 33, and outputs the selected value as data to be used for forming the encode subcode Q data 37.
Then, the encode subcode Q data 37 is latched for each frame, and a CRC calculator 39 calculates CRC data 38 for the thus-latched data, and appends the CRC data 38 to the encoded subcode Q data 37.
(Subcode P Data Generation)
The subcode P data is generated using the data for automatic generation 30 stored in the buffering area or is generated using the data stored in the paging area. Specifically, when ‘use PMSB’=1 (a predetermined bit in the 8-bit data stored in MODE is 1), a selector 43 for outputting the subcode P data outputs the value of PMSB (7 bits) as the encode subcode P data. When ‘use PMSB’=0 (the predetermined bit in the 8-bit data stored in MODE is 0), the selector 43 outputs the value of P (selected by a selector 44) stored in the paging area 45 as the encode subcode P data.
The other subcode data (R through W) is selected by selectors 42 and 44 from the 96 bytes in accordance with the value of an offset counter 41 which performs a counting operation every request (ESUBREQB) from the EFM encoder 40. The thus-selected one byte is outputted to the EFM encoder 40 as encode subcode serial data.
Thus, in the arrangement disclosed in Japanese Laid-Open Patent Application No. 10-302389, also at the time of encoding, the above-mentioned buffering area is utilized and the subcode P data and subcode Q data are automatically generated, and the data for this automatic generation is appended to the other subcode data when the data for the automatic generation is outputted. Thereby, decrease in the processing speed and complication of the circuit in the case where the subcode P data and subcode Q data are stored in the paging area can be avoided.
For Adr in the data for automatic generation 30 shown in FIG. 8, several types are set. However, the meanings are different due to differences in the standards of CD, CD-R, and so forth. For example, each of Adr0 and Adr1 means that the subcode data includes time data, Adr2 means that the subcode data includes UPC/EAN-Code, Disk Identification, Adr3 means that the subcode data includes ISR code (country code, year code, owner code, RID code, Skip Track), and Adr5 means that the subcode data includes a code indicating disk special information (Skip Time Internal) (see the so-called red book and orange book).
For example, a case where one UPC/EAN-Code (Adr2) is inserted every 100 pieces of time data is considered. Then, the commands written in the ‘POINTS’ of the buffering area shown in FIG. 9C are written as shown in FIG. 11A or 11B. In the command on the first line in FIG. 11A, Adr is Adr0, 1, and “100” is set in “REPEAT”. Therefore, the above-described processing of automatically generating the subcode Q data using the counter is repeated 100 times. After these 100 times of processing, jumping is performed to the address ‘1’ indicated by “POINT”. The command at the address ‘1’, to which the jumping is performed, is Adr2, that is, the command indicates generation of UPC/EAN-Code. In the generation of the subcode Q data of this Adr2, the above-described processing of automatic generation is not performed. That is, in the case where one UPC/EAN-Code (Adr2) is inserted every 100 pieces of time data, the automatic generation of the subcode Q data is repeated 100 times, and, then, is stopped. Then, after the generation of the subcode Q data of Adr2, an initial value is input to the counter again, and, then, the processing of automatic generation is started again in the generation of the subcode Q data of Adr0, 1.
This means that, even in a case where it is planed that a total of 300 pieces of time data are to be generated, it is not possible to write the command in which “REPEAT” is set to be “300”. As shown in FIG. 11A, it is forced to write the command in which “REPEAT” is set to be “100” for Adr0, 1, and the command for Adr2 alternately, repeatedly. As a result, the description of commands is complicated. Further, in a case where simplification of description is attempted as a result of commands having common Adr being collected as shown in FIG. 11B, description of destinations to which jumping is performed is complicated.
Further, there is the standard in which the subcode P data toggles at 2 Hz in a case where music data or the like is handled. Because one second corresponds to 75 frames (sectors), data setting of subcode P data of the data for automatic generation 30 is performed every 75/4 sectors. That is, it is necessary to count the number of sectors, and to access the memory at the time the predetermined number has been counted. In other words, although the processing of automatic generation of the subcode Q data can be performed 100 times as described above when the condition where the subcode P data toggles at 2 Hz is not set, the processing of automatic generation of the subcode Q data can not even be performed 100 times when the condition where the subcode P data toggles at 2 Hz is set.
The above-mentioned problems occur not only in the case where Adr is Adr2, but also in the case where Adr is Adr3 or Adr5.